1. Field of the Invention
The invention relates to electronic communication and, more particularly, to symbol-clock recovery in a digital receiver.
2. Description of the Related Art
Electronic communication is generally accomplished through a carrier wave that is modulated to bear data from a transmitting unit to a receiving unit. The transmission of digital data involves several steps, including partitioning the data into a sequence of symbols, modulating the carrier wave with the sequence of symbols to produce the transmitted signal, and propagating the transmitted signal through a communication channel. The received signal is received by the receiver which demodulates it to extract the received symbols. Finally, the receiver quantizes the symbols to reproduce the transmitted digital data.
An important component of the receiver is a symbol clock used in demodulating the received signal and quantizing the symbols. The symbol clock generates a signal at the symbol rate of the received signal. The symbol clock indicates the boundaries between symbols in the received signal, and is an important input to various elements in the receiver such as matched filters, differential decoders, and slicers. If the symbol clock signal deviates from the correct timing of the symbol boundaries, the function of all of these components is degraded, increasing the receiver's error rate. It is therefore helpful to have a system for evaluating the symbol clock and detecting drifts in its phase from the timing of the symbol sequence.
Prior-art symbol-timing recovery circuits use open-loop synchronizers, which use no feedback to the symbol clock, and closed-loop synchronizers, which test small shifts in the symbol timing for improved symbol synchronization and adjust the symbol clock accordingly. The closed-loop synchronizers, such as early/late-gate loops and tau-dither loops, generate error signals indicative of the phase offset between the symbol boundaries and the symbol clock. The early/late-gate loops depend on symbol transitions to generate the error signals. Hence, they are prone to drifting from the correct symbol timing when the received signal contains a run of repeated symbols. This problem is reduced by having better-balanced integrators or by using a tau-dither loop, but both of these measures add significantly to the complexity of the synchronizers.
Under certain conditions, such as when the symbol clock is derived from a frame clock or a spreading code chip clock, a relatively slow (requiring several symbol periods) measure of the symbol quality is adequate for providing the feedback to the symbol clock. A system built from simple circuit elements to provide this measure would be a valuable tool in the design of communications receivers.
Such a system could also be used to configure a receiver with an appropriate timing for its symbol clock. If a receiver derives its symbol clock from another clock that has the same frequency but has a phase offset from the symbol transitions, then this system for evaluating the symbol clock would provide a simple means for measuring the phase offset at the end of the manufacturing process. The receiver can then be configured to use the measured value as an initial estimate of the offset during future operation.